Projects

A full RTL weather station design targeting a 32.768 kHz clock on an FPGA. The system integrates multiple sensors and peripherals, all coordinated through a custom memory controller with a 4-way round-robin arbiter.

The SPI interface drives an MS5803-02BA pressure and temperature sensor. Raw ADC readings from the barometer are compensated using a sequence of PROM coefficients (C1–C6) following the MS5803 datasheet calibration procedure. A separate ADC-based wind vane module reads wind direction.

An LCD controller formats and displays live pressure, temperature, wind direction, and elapsed time. The memory controller manages read/write arbitration between all subsystems with no bus contention.

Verified using Cadence Xcelium with a behavioural testbench that models the SPI MISO responses of the MS5803, including PROM read and D1/D2 conversion phases.

A 4-stage pipelined hardware accelerator for the Nonlinear Energy Operator (NEO), computing ψ[n] = x[n−1]² − x[n]·x[n−2] on streaming input data.

The NEO is used in biomedical signal processing (e.g. spike detection in neural recordings) where real-time, low-latency computation matters. The pipeline processes one sample per clock cycle at full throughput after the initial fill latency.

Synthesised on a Cyclone IV E FPGA via Quartus Prime. Test vectors were generated in MATLAB using 4-bit signed fixed-point values and verified against the RTL output.

A full VLSI design flow for an 8-bit shift-and-add multiplier in TSMC 180nm technology. The project covered every stage from schematic and layout through RTL, synthesis, and test integration.

The control FSM has 11 states managing the shift-and-add algorithm. A tristate bus connects the datapath to shared resources. Scan chain (SDI/SDO/Test) was added for DFT, enabling full scan-based testing of all internal state.

Layout was done in Magic VLSI following TSMC 180nm design rules. Logic synthesis was performed with Synopsys Design Compiler, targeting area and timing constraints.

A 5-stage pipelined 32-bit RISC-V processor designed during an industry VLSI internship at Maven Silicon. The pipeline implements the standard fetch, decode, execute, memory, and writeback stages with hazard detection and forwarding logic.

During this project, a novel low-power ALU architecture was co-invented using enable gating to suppress switching activity in unused functional units. This work is now a filed patent.