Projects

Weather Station ASIC Design

Mar 2026 · SystemVerilog · Full ASIC Flow
Architecture Diagram →

A weather station ASIC targeting the AMS 0.35µm process, integrating Single Port SRAM, rain, wind direction, and wind speed sensors with both an 8-bit character LCD, and a 48x84 pixel LCD.

The LCD Controller formats and displays live rain, wind speed, wind direction, and elapsed time. The Memory Controller uses a request/grant interface to coordinate access to shared SRAM. Display accesses are prioritised to ensure low-latency framebuffer updates, while write requests from the rain and wind sensor modules are arbitrated using a round-robin policy. The system interfaces with an 8-kbit single-port SRAM macrocell for intermediate data storage.

The RTL was implemented in SystemVerilog and validated through the full ASIC design flow: verification with Cadence Xcelium, synthesis using Synopsys Design Compiler, place-and-route with Cadence Encounter, and post-layout processing in Cadence Virtuoso.

Custom Cell Library, Characterisation & Bitslice Multiplier

Dec 2025 · Magic VLSI, Python, SPICE, SystemVerilog · TSMC180
GitHub →

End-to-end hardware design & validation project spanning transistor-level cell design, automated characterisation, and system-level integration.

Developed a custom standard cell library (TSMC 180nm), including individually designed NAND gates and RD-type flip-flops.

Designed an 8-bit bitslice multiplier with an 11-state FSM and integrated scan chain for observability.

Built a Python-based framework to automate HSPICE simulations and generate databooks for analysing cell timing and behaviour.

Validated correctness and behaviour across abstraction levels from individual cells to full system integration.

NEO Accelerator

2025 · SystemVerilog · Cyclone IV E FPGA
GitHub →

A 4-stage pipelined hardware accelerator for the Nonlinear Energy Operator (NEO), computing ψ[n] = x[n−1]² − x[n]·x[n−2] on streaming input data.

The NEO is used in biomedical signal processing (e.g. spike detection in neural recordings) where real-time, low-latency computation matters. The pipeline processes one sample per clock cycle at full throughput after the initial fill latency.

Synthesised on a Cyclone IV E FPGA via Quartus Prime. Test vectors were generated in MATLAB using 4-bit signed fixed-point values and verified against the RTL output.

C++ Implementation of MiniAES

2025 · C++
GitHub →

MiniAES Implementation of C++, operates on 16-bit blocks & 16-bit keys.

The internal state is four 4-bit nibbles & both encryption and decryption are fully implemented. The encrypt path applies initial key addition, then two rounds of NibbleSub (4-bit S-box lookup), ShiftRow (p1/p3 swap), MixColumns (2x2 matrix over GF (24) modulo x4+x+1), and key addition; and the decrypt path reverses this utilising inverse S-box. The key schedule derives three 16-bit round keys (K0 - K2) from the master key via nibble-level expansion with S-box & RCON injection.

32-bit RISC-V Processor

Maven Silicon Internship · 2023

A 5-stage pipelined 32-bit RISC-V processor designed during an industry VLSI internship at Maven Silicon. The pipeline implements the standard fetch, decode, execute, memory, and writeback stages with hazard detection and forwarding logic.