CV

Experience

VLSI Design Intern Maven Silicon · 2023

32-bit RISC-V processor design (5-stage pipeline). Co-invented a low-power ALU architecture using enable gating — now a filed patent.

Education

MSc Microelectronics Systems Design University of Southampton · 2024–25

EDA tools: Cadence Xcelium, Synopsys Design Compiler, Magic VLSI. Modules include secure hardware, VLSI design, and computer architecture.

BTech Electronics & Instrumentation Engineering VIT Vellore · 8.15 CGPA

Digital electronics, embedded systems, signal processing.

Skills

Languages SystemVerilog, Verilog, C++, MATLAB, Python
EDA Tools Cadence Xcelium, Synopsys DC, Quartus Prime, Magic VLSI, HSPICE
Techniques RTL design, functional verification, FSM design, pipelining, DFT/scan chain